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Disambiguation of "Ye, Le"

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Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.

, , , , , , , , , and . CICC, page 1-2. IEEE, (2024)

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Fei Ye

Ye Hu

Ye Chen

Ying Ye

Wei Ye

 

Other publications of authors with the same name

2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT., , , , and . ISCAS, page 1-5. IEEE, (2020)SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter., , , , and . ISCAS, page 749-752. IEEE, (2013)30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing., , , , , , , , , and 1 other author(s). ISSCC, page 484-486. IEEE, (2024)5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array., , , , , , , , and . ISSCC, page 72-74. IEEE, (2021)An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique., , , , , , , , , and 4 other author(s). ISSCC, page 372-374. IEEE, (2022)A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing., , , , , , , , , and 3 other author(s). ISSCC, page 140-141. IEEE, (2023)A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology., , , , , , , , , and . ESSCIRC, page 121-124. IEEE, (2023)A single-chip CMOS UHF RFID Reader transceiver for mobile applications., , , , , , , , , and 2 other author(s). ESSCIRC, page 228-231. IEEE, (2009)Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 1160-1170 (2021)An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (8): 3075-3088 (2023)