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Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.

, , , and . CGO, page 175-188. IEEE Computer Society, (2004)

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SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations., , , and . MICRO, page 425-436. IEEE Computer Society, (2012)Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs., , , , , , , , , and . FCCM, page 34-40. IEEE, (2023)Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations., , , , , and . HPCA, page 689-702. IEEE, (2020)Expressing Sparse Matrix Computations for Productive Performance on Spatial Architectures.. CoRR, (2018)Register allocation for software pipelined multi-dimensional loops., , and . PLDI, page 154-167. ACM, (2005)Just-In-Time Software Pipelining., , , and . CGO, page 11. ACM, (2014)Embedding a DSL in SYCL for Productive and Performant Tensor Computing on Heterogeneous Devices., and . IWOCL, page 30:1. ACM, (2022)Multi-dimensional Kernel Generation for Loop Nest Software Pipelining., , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 311-322. Springer, (2006)POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations., , , , , and . FPGA, page 199-210. ACM, (2024)Leveraging Hardware Probes and Optimizations for Accelerating Fuzz Testing of Heterogeneous Applications., , , , and . ESEC/SIGSOFT FSE, page 1101-1113. ACM, (2023)