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A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications., , , , , и . ISCAS, стр. 1-4. IEEE, (2020)A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC., и . ISCAS, стр. 1-5. IEEE, (2019)A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS., , , и . APCCAS, стр. 30-33. IEEE, (2018)A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration., и . ESSCIRC, стр. 301-304. IEEE, (2019)A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz., , и . ISCAS, стр. 1-4. IEEE, (2017)RFI mitigating receiver back-end for radiometers., , , , и . IGARSS, стр. 1255-1258. IEEE, (2017)Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications., , , , , , и . NEWCAS, стр. 1-4. IEEE, (2016)A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS., , , , , и . ISCAS, стр. 1-4. IEEE, (2019)An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology., , , , , , и . LASCAS, стр. 1-4. IEEE, (2020)A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology., и . ESSCIRC, стр. 99-102. IEEE, (2019)