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s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin, H. Zhang, N. Narang, K. Tan, G. Zhang, Y. Frans, and K. Chang. IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)

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Parag Goyal

Parag Narvekar

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A new gain controllable on-chip active balun for 5 GHz direct conversion receiver.M. Rajashekharaiah, P. Upadhyaya, D. Heo, and Y. Chen. ISCAS (5), page 5115-5118. IEEE, (2005)A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET.M. Raj, P. Upadhyaya, Y. Frans, and K. Chang. VLSI Circuits, page 1-2. IEEE, (2016)A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.K. Chan, K. Tan, Y. Frans, J. Im, P. Upadhyaya, S. Lim, A. Roldan, N. Narang, C. Koay, H. Zhao and 1 other author(s). A-SSCC, page 233-236. IEEE, (2016)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.J. Savoj, H. Aslanzadeh, D. Carey, M. Erett, W. Fang, Y. Frans, K. Hsieh, J. Im, A. Jose, D. Turker and 3 other author(s). CICC, page 1-4. IEEE, (2014)Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.J. Savoj, K. Hsieh, P. Upadhyaya, F. An, J. Im, X. Jiang, J. Kamali, K. Lai, Z. Wu, E. Alon and 1 other author(s). CICC, page 1-4. IEEE, (2012)A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.C. Poon, W. Zhang, J. Cho, S. Ma, Y. Wang, Y. Cao, A. Laraba, E. Ho, W. Lin, Z. Wu and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.C. Poon, W. Zhang, J. Cho, S. Ma, Y. Wang, Y. Cao, A. Laraba, E. Ho, W. Lin, Z. Wu and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 1199-1210 (2022)A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications.C. Xie, M. Raj, A. Joshi, Z. Mohammed, G. Saha, Z. Wang, P. Upadhyaya, and Y. Frans. OFC, page 1-3. IEEE, (2024)A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.J. Savoj, K. Hsieh, F. An, J. Gong, J. Im, X. Jiang, A. Jose, V. Kireev, S. Lim, A. Roldan and 4 other author(s). IEEE J. Solid State Circuits, 48 (11): 2582-2594 (2013)6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, A. Chou, T. Cronin, K. Geary, S. McLeod, L. Zhou and 7 other author(s). ISSCC, page 114-115. IEEE, (2017)

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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Please choose a person to relate this publication to

Parag Goyal

Parag Narvekar

Nikos Paragios

Parag Mogre

Parag Kinge

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Upadhyaya, Parag"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Please choose a person to relate this publication to

Parag Goyal

Parag Narvekar

Nikos Paragios

Parag Mogre

Parag Kinge

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.