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Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation.

, , , , , and . DFT, page 1-4. IEEE, (2020)

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The Effect of Wire Length Minimization on Yield., , and . DFT, page 97-105. IEEE Computer Society, (1994)Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays., and . ICPP (1), page 123-127. CRC Press, (1991)Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems., and . IEEE Trans. Computers, 40 (9): 1024-1033 (1991)Incorporating Yield Enhancement into the Floorplanning Process., and . IEEE Trans. Computers, 49 (6): 532-541 (2000)Identification of in-field defect development in digital image sensors., , , , , and . Digital Photography, volume 6502 of SPIE Proceedings, page 65020Y. SPIE, (2007)Effective analytical delay model for transistor sizing., and . ASP-DAC, page 387-392. ACM Press, (2005)On the effect of floorplanning on the yield of large area integrated circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (1): 3-14 (1997)Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard., , , , and . IEEE Trans. Computers, 52 (4): 492-505 (2003)Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation., , , , , and . RFIDSec, volume 7055 of Lecture Notes in Computer Science, page 48-60. Springer, (2011)Countermeasures against fault attacks on software implemented AES: effectiveness and cost., , , , and . WESS, page 7. ACM, (2010)