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Disambiguation of "Chang, Muya"

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29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.

, , , , , and . ISSCC, page 404-406. IEEE, (2021)

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Vandana Muyal

Fu-Chang Chang

Sheng-Chia Chang

William Ockham's view on human capability. Uni Frankfurt Main, (2009)

Doo-Bong Chang

Belinda Chang

 

Other publications of authors with the same name

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking., , , , , , , , , and 1 other author(s). ISSCC, page 426-427. IEEE, (2023)A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture., , , , and . ICASSP, page 1493-1497. IEEE, (2019)OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers., , , and . IEEE J. Solid State Circuits, 55 (3): 629-638 (2020)A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , and . ISSCC, page 1-3. IEEE, (2022)A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics., , and . ISSCC, page 222-224. IEEE, (2019)29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification., , , , , and . ISSCC, page 404-406. IEEE, (2021)27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation., , , , , , , , , and 4 other author(s). ISSCC, page 424-426. IEEE, (2020)