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Escape Routing For Dense Pin Clusters In Integrated Circuits.. DAC, page 49-54. IEEE, (2007)Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 84-95 (2008)A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2784-2794 (2006)An improved benchmark suite for the ISPD-2013 discrete cell sizing contest., , , , , and . ISPD, page 168-170. ACM, (2013)Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms.. ISPD, page 39. ACM, (2019)Algorithms for simultaneous escape routing and Layer assignment of dense PCBs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (8): 1510-1522 (2006)Optimal routing algorithms for pin clusters in high-density multichip modules., , and . ICCAD, page 767-774. IEEE Computer Society, (2005)A provably good algorithm for high performance bus routing., and . ICCAD, page 830-837. IEEE Computer Society / ACM, (2004)Gate sizing and device technology selection algorithms for high-performance industrial designs., , and . ICCAD, page 724-731. IEEE Computer Society, (2011)Algorithmic study of single-layer bus routing for high-speed boards., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (3): 490-503 (2006)