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Hardware Accelerator Design for Data Centers., , , , , and . ICCAD, page 770-775. IEEE, (2015)Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits., , , , , , and . ICCAD, page 1-9. IEEE, (2021)GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits., , , , , , , , , and . DATE, page 55-60. IEEE, (2020)Testing asynchronous circuits: A survey., , and . Integr., 19 (3): 111-131 (1995)A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation., , and . FPL, page 335-342. IEEE Computer Society, (2018)The ISPD-2012 discrete cell sizing contest and benchmark suite., , , , , and . ISPD, page 161-164. ACM, (2012)Comparative Analysis of Conventional and Statistical Design Techniques., , , , , and . DAC, page 238-243. IEEE, (2007)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement., , , , , , and . DATE, page 148-153. IEEE, (2022)Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators., , , , , , and . ASP-DAC, page 475-482. ACM, (2023)Energy Efficient Architecture for Graph Analytics Accelerators., , , , , , and . ISCA, page 166-177. IEEE Computer Society, (2016)