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Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification.

, , , and . IEEE Des. Test, 34 (5): 5-6 (2017)

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Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery., , , and . DAC, page 34:1-34:6. ACM, (2017)An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology., , , , and . ASP-DAC, page 163-168. IEEE, (2012)Introduction to special section on verification challenges in the concurrent world., , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 19:1-19:3 (2012)Enhancing signal controllability in functional test-benches through automatic constraint extraction., , and . ITC, page 1-10. IEEE Computer Society, (2007)Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning., , and . ITC, page 1-8. IEEE Computer Society, (2009)Full chip false timing path identification: applications to the PowerPCTM microprocessors., , , and . DATE, page 514-519. IEEE Computer Society, (2001)A Mechanized Refinement Framework for Analysis of Custom Memories., and . FMCAD, page 239-242. IEEE Computer Society, (2007)A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications., , , and . HLDVT, page 134-141. IEEE Computer Society, (2001)Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling., , , , and . MTV, page 3-8. IEEE Computer Society, (2009)Striking a balance between SoC security and debug requirements., and . SoCC, page 368-373. IEEE, (2016)