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Testability analysis based on structural and behavioral information., и . VTS, стр. 139-146. IEEE Computer Society, (1993)Impact of high level functional constraints on testability., , и . VTS, стр. 309-312. IEEE Computer Society, (1993)Design for Testability Using Architectural Descriptions., , и . ITC, стр. 752-761. IEEE Computer Society, (1992)ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults., и . ITC, стр. 729-738. IEEE Computer Society, (1991)Architectural Level Test Generation and Fault Simulation. University of Illinois Urbana-Champaign, USA, (1992)A comparative study of design for testability methods using high-level and gate-level descriptions., , и . ICCAD, стр. 620-624. IEEE Computer Society / ACM, (1992)Hierarchical Test Generation under Intensive Global Functional Constraints., и . DAC, стр. 261-266. IEEE Computer Society Press, (1992)An Architectural Level Test Generator for a Hierarchical Design Environment., и . FTCS, стр. 44-51. IEEE Computer Society, (1991)An Instruction Sequence Assembling Methodology for Testing Microprocessors., и . ITC, стр. 49-58. IEEE Computer Society, (1992)A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation., и . ICCAD, стр. 458-461. IEEE Computer Society, (1991)