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Disambiguation of "Rawat, Harsh"

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A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications.

, , , , , , , , , , , , and . ISSCC, page 260-261. IEEE, (2023)

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Rawat Siripokarpirom

Harsh Dweep

Anuj Rawat

Rahul Ramesh Harshe

Mandar Harshe

 

Other publications of authors with the same name

A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications., , , , , , , , , and 3 other author(s). ISSCC, page 260-261. IEEE, (2023)Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS., , , , , , , , and . ICECS, page 1-6. IEEE, (2021)A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators., , and . AICAS, page 459-462. IEEE, (2022)3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS., , , , , and . ISCAS, page 1546-1550. IEEE, (2022)Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI., , , , , and . VLSID, page 228-233. IEEE, (2022)A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI., , and . SoCC, page 310-315. IEEE, (2015)Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology., , and . SoCC, page 1-6. IEEE, (2017)A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology., , and . VLSID, page 121-126. IEEE, (2023)