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Disambiguation of "Natarajan, Sreedhar"

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Semantic Information Modeling for Emerging Applications in Smart Grid

, , , and . IEEE International Conference on Information Technology : New Generations (ITNG), page 775--782. (2012)
DOI: 10.1109/ITNG.2012.150

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Sreedhar Madishetti

Kasyap Natarajan

Paruthiure Natarajan

Balamurali Sreedhar

Natarajan Thiagarajan

 

Other publications of authors with the same name

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme., , , , , , , , , and 2 other author(s). ISSCC, page 332-333. IEEE, (2014)Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology., , , , , , , , and . ISSCC, page 224-225. IEEE, (2013)A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 270-271. IEEE, (2008)Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI., and . ASP-DAC/VLSI Design, page 297-298. IEEE Computer Society, (2002)A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Towards Data-driven Demand-Response Optimization in a Campus Microgrid, , , , , and . Workshop On Embedded Sensing Systems For Energy-Efficiency In Buildings (BuildSys), page 41--42. ACM, (2011)Demo.PD-SOI and FD-SOI: a comparison of circuit performance., and . ICECS, page 25-28. IEEE, (2002)Leakage Reduction techniques in a 0.13um SRAM Cell., , , and . VLSI Design, page 215-221. IEEE Computer Society, (2004)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications., , , , , , , , , and 5 other author(s). ISSCC, page 316-317. IEEE, (2013)Semantic Information Integration and Processing for Demand Response Optimization, , , and . Southern California Smart Grid Research Symposium (SoCalSGS), (2011)Poster.