From post

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers.

, , , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs., , , , , , и . ESSCIRC, стр. 377-380. IEEE, (2022)A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications., , , , , , и . ESSCIRC, стр. 355-358. IEEE, (2005)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 66-68. IEEE, (2012)F1: Designing secure systems: Manufacturing, circuits and architectures., , , , , , и . ISSCC, стр. 492-494. IEEE, (2016)A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer., , , , , , , , и . ISSCC, стр. 478-480. IEEE, (2022)Circuit techniques for low-power CMOS GSI., , , и . ISLPED, стр. 193-196. IEEE, (1996)A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction., , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2021)Improving compute in-memory ECC reliability with successive correction., , , , , , , и . DAC, стр. 745-750. ACM, (2022)8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator., , , , , и . ISSCC, стр. 142-143. IEEE, (2017)Low power and high performance design challenges in future technologies., и . ACM Great Lakes Symposium on VLSI, стр. 1-6. ACM, (2000)