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Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations., , and . J. Embed. Comput., 2 (1): 15-34 (2006)Parallel Factorization of Boolean Polynomials., , , , , and . Ershov Informatics Conference, volume 11964 of Lecture Notes in Computer Science, page 80-94. Springer, (2019)Hardware Solution for Real-Time Face Recognition., , , , , and . VLSID, page 81-86. IEEE Computer Society, (2015)Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic., , , and . VLSID, page 415-420. IEEE Computer Society, (2016)A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design., , , , , , and . VLSID, page 64-69. IEEE, (2019)Applying Modified Householder Transform to Kalman Filter., , , , , , and . VLSID, page 431-436. IEEE, (2019)An Architectural View of the Entities Required for Execution of Task in Pervasive Space., , , , and . FTDCS, page 37-43. IEEE Computer Society, (2004)A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support., , , and . ISED, page 45-50. IEEE Computer Society, (2011)On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort., , and . WMPI, page 88-95. ACM, (2004)Power-performance trade-off using pipeline delays., , and . ASP-DAC, page 384-386. IEEE Computer Society, (2004)