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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)

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Future silicon technology.. ESSCIRC, page 1-6. IEEE, (2012)Vision-Based Object-Centric Safety Assessment Using Fuzzy Inference: Monitoring Struck-By Accidents with Moving Objects., , and . J. Comput. Civ. Eng., (2016)Emerging memory technologies., , , and . CICC, page 423-426. IEEE, (2005)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)The future outlook of memory devices., and . ESSCIRC, page 47. IEEE, (2007)Electrical properties of highly reliable 32Mb FRAM with advanced capacitor technology., , , , , , , , and . Microelectron. Reliab., 45 (7-8): 1150-1153 (2005)A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput., , , , , , , , , and 17 other author(s). ISSCC, page 472-616. IEEE, (2007)1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture., , , , , , , , , and 5 other author(s). ISSCC, page 128-129. IEEE, (2009)A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS., , , , , and . ISSCC, page 396-398. IEEE, (2012)1.1 Silicon technologies and solutions for the data-driven world.. ISSCC, page 1-7. IEEE, (2015)