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Disambiguation of "Taneja, Sachin"

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A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.

, , , , , and . IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)

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Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Kumar

Sachin Chhatwani

 

Other publications of authors with the same name

ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security., , and . ISSCC, page 498-500. IEEE, (2021)A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS., , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 1106-1116 (2023)A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm., , , and . A-SSCC, page 301-304. IEEE, (2017)Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm., and . ISCAS, page 1-5. IEEE, (2020)A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2024)A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology., , , and . SoCC, page 304-309. IEEE, (2015)PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion., and . IEEE J. Solid State Circuits, 56 (7): 2182-2192 (2021)