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Disambiguation of "Mathew, Sanu K."

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A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.

, , , , , and . IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)

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Muhammad Sanusi

Rebecca Mathew

Stanley Mathew

Mathew Joseph

Mathew Mandapathil

 

Other publications of authors with the same name

A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit., , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 26-37 (2007)Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks., , , , , , , , and . CICC, page 1-2. IEEE, (2021)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2022)A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS., , , , , and . IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS., , , , and . ISSCC, page 306-308. IEEE, (2024)Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms.. ACM Great Lakes Symposium on VLSI, page 403. ACM, (2022)