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A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply., , and . ISCAS, page 1-4. IEEE, (2019)A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing., , , and . ISCAS, page 169-172. IEEE, (2013)26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience., , and . ISSCC, page 438-439. IEEE, (2016)A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference., , , , and . A-SSCC, page 1-3. IEEE, (2021)A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power., , , , , and . ISSCC, page 142-144. IEEE, (2018)A 0.13µm CMOS ΔΣ PLL FM transmitter., , , , , , , and . NORCHIP, page 1-4. IEEE, (2011)A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency., , , and . ISSCC, page 214-216. IEEE, (2022)A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer., , , and . ISCAS, page 1-4. IEEE, (2019)An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording., , , , and . CICC, page 1-2. IEEE, (2021)A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity., , and . ISSCC, page 414-416. IEEE, (2019)