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Disambiguation of "Müller, Silvia M."

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Pain versus Gain in the Hardware Design of FPUs and Supercomputers.

, , , , , and . IEEE Symposium on Computer Arithmetic, page 39. IEEE Computer Society, (2005)

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Silvia Müller

Silvia Müller

Silvia Müller

Silvia Müller

Silvia Melitta Müller

 

Other publications of authors with the same name

Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Energy Efficiency Boost in the AI-Infused POWER10 Processor., , , , , , , , , and 16 other author(s). ISCA, page 29-42. IEEE, (2021)On the Scheduling of Variable Latency Functional Units.. SPAA, page 148-154. ACM, (1999)Conflict-Free Access to Multiple Single-Ported Register Files., and . IPPS, page 672-678. IEEE Computer Society, (1997)Efficient mapping of randomly sparse neural networks on parallel vector supercomputers., and . SPDP, page 170-177. IEEE Computer Society, (1994)Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers., and . IFIP Congress, page 459-460. North-Holland/IFIP, (1989)The IBM zEnterprise-196 Decimal Floating-Point Accelerator., , , and . IEEE Symposium on Computer Arithmetic, page 139-146. IEEE Computer Society, (2011)Novel hardware & software design for mathematical and AI acceleration., , and . CASCON, page 268-269. ACM, (2020)Making the Original Scoreboard Mechanism Deadlock Free., and . ISTCS, page 92-99. IEEE Computer Society, (1996)