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Pain versus Gain in the Hardware Design of FPUs and Supercomputers.

, , , , , and . IEEE Symposium on Computer Arithmetic, page 39. IEEE Computer Society, (2005)

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FPU Implementations with Denormalized Numbers., , and . IEEE Trans. Computers, 54 (7): 825-836 (2005)Minimum test patterns for residue networks., , , and . DAC, page 278-284. ACM, (1971)P6 Binary Floating-Point Unit., , , and . IEEE Symposium on Computer Arithmetic, page 77-86. IEEE Computer Society, (2007)Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor., , and . IEEE Symposium on Computer Arithmetic, page 116-123. IEEE Computer Society, (1999)Avoiding Unknown States When Scanning Mutually Exclusive Latches., and . ITC, page 311-318. IEEE Computer Society, (1995)Pain versus Gain in the Hardware Design of FPUs and Supercomputers., , , , , and . IEEE Symposium on Computer Arithmetic, page 39. IEEE Computer Society, (2005)Hardware Implementations of Denormalized Numbers., , and . IEEE Symposium on Computer Arithmetic, page 70-78. IEEE Computer Society, (2003)A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension., , , , , , , , and . IEEE Symposium on Computer Arithmetic, page 12-. IEEE Computer Society, (1999)Leading Zero Anticipation and Detection-A Comparison of Methods., and . IEEE Symposium on Computer Arithmetic, page 7-12. IEEE Computer Society, (2001)