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Disambiguation of "Rao, Rahul M."

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3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.

, , , , , , , , , , , , , and . ISSCC, page 50-51. IEEE, (2017)

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Rahul M S

Rahul Gupta

Rahul Dewan

Rahul Bahulikar

Rahul Ray

 

Other publications of authors with the same name

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies., , and . ESSCIRC, page 313-316. IEEE, (2003)On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit., , , , and . VLSI Design, page 143-149. IEEE Computer Society, (2008)Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies., , , and . ISCAS, page 384-387. IEEE, (2008)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)Leakage and leakage sensitivity computation for combinational circuits., , , , , , and . ISLPED, page 96-99. ACM, (2003)A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation., , and . ISLPED, page 45-50. ACM, (2009)Virtual logic netlist: Enabling efficient RTL analysis., , , and . ISQED, page 571-576. IEEE, (2015)Frequency estimation by linear prediction., , , and . ICASSP, page 352-356. IEEE, (1978)A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement., , and . ISSCC, page 412-413. IEEE, (2008)Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization., , , , and . ISQED, page 88-93. IEEE Computer Society, (2005)