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3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.

, , , , , , , , , , , , , and . ISSCC, page 50-51. IEEE, (2017)

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5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)NetDER: An Architecture for Reasoning About Malicious Behavior., , , and . Inf. Syst. Frontiers, 23 (1): 185-201 (2021)Leveraging Probabilistic Existential Rules for Adversarial Deduplication., , , and . PRUV@IJCAR, volume 2157 of CEUR Workshop Proceedings, CEUR-WS.org, (2018)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)Improvements to the Robust Transform Based on the Weighted Median Operator Algorithm., , and . CLEI Selected Papers, volume 349 of Electronic Notes in Theoretical Computer Science, page 81-102. Elsevier, (2020)A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor., , , , , , , , , and 3 other author(s). ISSCC, page 344-345. IEEE, (2010)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM J. Res. Dev., (2015)Power-constrained high-frequency circuits for the IBM POWER6 microprocessor., , , , , , and . IBM J. Res. Dev., 51 (6): 715-732 (2007)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)Pulsed Neural Network Plus Parallel Multi-core Approach to Solve Efficiently Big Shortest Path Problems., , , , and . MICAI, volume 11835 of Lecture Notes in Computer Science, page 200-211. Springer, (2019)