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A Framework to Model Branch Prediction for WCET Analysis, и . (июня 2002)Short version of: A Framework to Model Branch Prediction for WCET Analysis, Tulika Mitra, Abhik Roychoudhury, 2nd Workshop on Worst Case Execution Time Analysis (WCET), Austria, June 2002. Also available as NUS Technical Report 11-01. One of Author's homepage: http://www.comp.nus.edu.sg/~abhik/.Efficient custom instructions generation for system-level design., , и . FPT, стр. 445-448. IEEE, (2010)Analyzing Loop Paths for Execution Time Estimation., , и . ICDCIT, том 3816 из Lecture Notes in Computer Science, стр. 458-469. Springer, (2005)Instruction-set customization for real-time embedded systems., и . DATE, стр. 1472-1477. EDA Consortium, San Jose, CA, USA, (2007)Design Space exploration of FPGA-based accelerators with multi-level parallelism., , , , , и . DATE, стр. 1141-1146. IEEE, (2017)An efficient framework for dynamic reconfiguration of instruction-set customization., , и . CASES, стр. 135-144. ACM, (2007)Static analysis for fast and accurate design space exploration of caches., и . CODES+ISSS, стр. 103-108. ACM, (2008)Cache modeling in probabilistic execution time analysis., и . DAC, стр. 319-324. ACM, (2008)Efficient detection and exploitation of infeasible paths for software timing analysis., , , и . DAC, стр. 358-363. ACM, (2006)Exploiting forwarding to improve data bandwidth of instruction-set extensions., , и . DAC, стр. 43-48. ACM, (2006)