Author of the publication

Efficient detection and exploitation of infeasible paths for software timing analysis.

, , , and . DAC, page 358-363. ACM, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Framework to Model Branch Prediction for WCET Analysis, and . (June 2002)Short version of: A Framework to Model Branch Prediction for WCET Analysis, Tulika Mitra, Abhik Roychoudhury, 2nd Workshop on Worst Case Execution Time Analysis (WCET), Austria, June 2002. Also available as NUS Technical Report 11-01. One of Author's homepage: http://www.comp.nus.edu.sg/~abhik/.Analyzing Loop Paths for Execution Time Estimation., , and . ICDCIT, volume 3816 of Lecture Notes in Computer Science, page 458-469. Springer, (2005)Application-Specific Processors.. Handbook of Hardware/Software Codesign, (2017)An efficient framework for dynamic reconfiguration of instruction-set customization., , and . Des. Autom. Embed. Syst., 13 (1-2): 91-113 (2009)Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs., , , , , , and . CoRR, (2023)Static analysis for fast and accurate design space exploration of caches., and . CODES+ISSS, page 103-108. ACM, (2008)Efficient custom instructions generation for system-level design., , and . FPT, page 445-448. IEEE, (2010)An efficient framework for dynamic reconfiguration of instruction-set customization., , and . CASES, page 135-144. ACM, (2007)Integrated instruction cache analysis and locking in multitasking real-time systems., , and . DAC, page 147:1-147:10. ACM, (2013)Cache modeling in probabilistic execution time analysis., and . DAC, page 319-324. ACM, (2008)