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Disambiguation of "Shen, Shan"

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RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.

, , , , and . MEMSYS, page 451-458. ACM, (2019)

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Shan-Shan Zhan

Jiening Shan

Yunsheng Shan

Yao Shan

Jianfeng Shan

 

Other publications of authors with the same name

A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1139-1143 (March 2023)A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (4): 1223-1234 (April 2023)TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages., , , , , , and . CoRR, (2019)Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation., , , , and . ASP-DAC, page 339-345. ACM, (2023)TYMER: A Yield-based Performance Model for Timing-speculation SRAM., , , , , and . DAC, page 1-6. IEEE, (2020)SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits., , and . ISQED, page 1-7. IEEE, (2024)A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2197-2209 (2021)A Behavior Study of the Effects of Visual Feedback on Motor Output., , , , , , and . EMBC, page 1273-1276. IEEE, (2006)Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs., , , , , and . ACM Great Lakes Symposium on VLSI, page 440-445. ACM, (2024)RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism., , , , and . MEMSYS, page 451-458. ACM, (2019)