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Disambiguation of "Joshi, Rajiv V."

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Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

, , , , , , , , , , , , , , , , , and . CoRR, (2023)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Rajiv Trehan

Rajiv Kumar

Paneerselvam Rajiv

Jidnyasa Joshi

Rajiv Grover

 

Other publications of authors with the same name

Design Considerations and Implementation of a High Performance Dynamic Register File., and . VLSI Design, page 526-531. IEEE Computer Society, (1999)Design Of Provably Correct Storage Arrays., , and . VLSI Design, page 196-. IEEE Computer Society, (2001)A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability., , , , , and . DAC, page 63:1-63:6. ACM, (2014)Efficient analog circuit optimization using sparse regression and error margining., , , , and . ISQED, page 410-415. IEEE, (2016)Design technology co-optimization for 10 nm and beyond., and . CICC, page 1. IEEE, (2014)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 534-543 (2015)Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction"., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1380 (2015)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation., , , , , , , , , and 14 other author(s). DATE, page 13-16. IEEE, (2022)Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture., , , , and . AICAS, page 1-5. IEEE, (2023)