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Implementation of a radix-2k fixed-point pipeline FFT processor with optimized word length scheme.

L. Pang, S. Dong, L. Jin, C. Yang, B. Li, Y. Xie, Y. Xie, and H. Chen. IEICE Electron. Express, 16 (13): 20190181 (2019)

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Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Mixed-Precision Quantization for CNN-Based Remote Sensing Scene Classification.X. Wei, H. Chen, W. Liu, and Y. Xie. IEEE Geosci. Remote. Sens. Lett., 18 (10): 1721-1725 (2021)Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm.Y. Xie, W. Yu, N. Zhang, H. Chen, and Y. Xie. DFT, page 1-4. IEEE, (2023)A new reconfigurable methodology to implement the 8-bit linear quantization for real-time SAR.J. Wang, Y. Wang, S. Xing, B. Li, Y. Xie, P. Nie, and K. Tang. ISCIT, page 171-174. IEEE, (2016)Spatio-Temporal Pruning for Training Ultra-Low-Latency Spiking Neural Networks in Remote Sensing Scene Classification.J. Li, M. Xu, H. Chen, W. Liu, L. Chen, and Y. Xie. Remote. Sens., 16 (17): 3200 (September 2024)Constrained Optimization of FPGA Design for Spaceborne InSAR Processing.J. Li, M. Xu, Y. Xie, and H. Chen. Remote. Sens., 14 (19): 4713 (2022)A SoPC based Fixed Point System for Spaceborne SAR Real-Time Imaging Processing.B. Li, C. Li, Y. Xie, L. Chen, H. Shi, and Y. Deng. HPEC, page 1-6. IEEE, (2018)Efficient and Flexible 2-D Data Controller for SAR Imaging System.T. Sun, Y. Xie, B. Li, H. Chen, X. Liu, and L. Chen. HPEC, page 1-6. IEEE, (2018)An FPGA-Based Balanced and High-Efficiency Two-Dimensional Data Access Technology for Real-Time Spaceborne SAR.T. Sun, B. Li, X. Liu, and Y. Xie. CSPS (3), volume 517 of Lecture Notes in Electrical Engineering, page 724-732. Springer, (2018)Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism.Y. Xie, T. Qiao, Y. Xie, and H. Chen. Frontiers Comput. Neurosci., (September 2023)An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC.Y. Xie, H. Chen, Y. Xie, C. Mao, and B. Li. FPT, page 370-373. IEEE, (2018)

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Disambiguation of "Xie, Yizhuang"

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Implementation of a radix-2k fixed-point pipeline FFT processor with optimized word length scheme.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Yizhuang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Implementation of a radix-2k fixed-point pipeline FFT processor with optimized word length scheme.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Implementation of a radix-2k fixed-point pipeline FFT processor with optimized word length scheme.