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16 years ago by @brightbyte
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1FNOCEE: A framework for NoC evaluation by FPGA-based emulation
D. Pfefferkorn, A. Schmider, G. Payá-Vayá, M. Neuenhahn, and H. Blume. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, page 86-95. (July 2015)
9 years ago by @imsl3s
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2Fault-tolerant routing for on-chip network without using virtual channels
P. Ren, Q. Meng, X. Ren, and N. Zheng. Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, page 1-6. (June 2014)
10 years ago by @eberle18
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2Packet logging mechanism for adaptive online fault detection on Network-on-Chip
L. Loo, C. Ooi, V. Liew, Y. Hau, and M. Marsono. Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, page 1760-1763. (June 2014)
10 years ago by @eberle18
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1A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures
L. Liu, C. Wu, C. Deng, S. Yin, Q. Wu, J. Han, and S. Wei. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, PP (99): 1-1 (2014)
10 years ago by @eberle18
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2Test Configurations for Diagnosing Faulty Links in NoC Switches
J. Raik, R. Ubar, and V. Govind. Test Symposium, 2007. ETS '07. 12th IEEE European, page 29-34. (May 2007)
10 years ago by @eberle18
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2On-line fault detection and location for NoC interconnects
C. Grecu, A. Ivanov, R. Saleh, E. Sogomonyan, and P. Pande. On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International, page 6 pp.-. (2006)
10 years ago by @eberle18
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2Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks
Z. Shi, and A. Burns. Real-Time Systems, 2009. ECRTS '09. 21st Euromicro Conference on, page 3-12. (July 2009)
10 years ago by @eberle18
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1Schedulability Analysis and Task Mapping for Real-time On-chip Communication
Z. Shi, and A. Burns. Real-Time Syst., 46 (3): 360--385 (December 2010)
10 years ago by @eberle18
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1Smart Reliable Network-on-Chip
C. Killian, C. Tanougast, F. Monteiro, and A. Dandache. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 22 (2): 242-255 (February 2014)
10 years ago by @eberle18
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1Crosstalk- and SEU-Aware Networks on Chips
A. Frantz, M. Cassel, F. Kastensmidt, E. Cota, and L. Carro. Design Test of Computers, IEEE, 24 (4): 340-350 (July 2007)
10 years ago by @eberle18
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2Low Power Error Resilient Encoding for On-Chip Data Buses
D. Bertozzi, L. Benini, and G. de Micheli. Proceedings of the Conference on Design, Automation and Test in Europe, page 102--. Washington, DC, USA, IEEE Computer Society, (2002)
10 years ago by @eberle18
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2Crosstalk avoidance coding for reliable data transmission of network on chips
Z. Shirmohammadi, and S. Miremadi. System on Chip (SoC), 2013 International Symposium on, page 1-4. (October 2013)
10 years ago by @eberle18
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1Markovian Models Based Stochastic Communication in Networks-in-Package
V. Sehgal. Parallel and Distributed Systems, IEEE Transactions on, PP (99): 1-1 (2014)
10 years ago by @eberle18
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1Networks on chips: a new SoC paradigm
L. Benini, and G. De Micheli. Computer, 35 (1): 70-78 (January 2002)
10 years ago by @eberle18
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2Powering Networks on Chips: Energy-efficient and Reliable Interconnect Design for SoCs
L. Benini, and G. De Micheli. Proceedings of the 14th International Symposium on Systems Synthesis, page 33--38. New York, NY, USA, ACM, (2001)
10 years ago by @eberle18
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2A brief overview of the challenges of the multicore roadmap
J. Collet. Mixed Design of Integrated Circuits Systems (MIXDES), 2014 Proceedings of the 21st International Conference, page 22-29. (June 2014)
10 years ago by @eberle18
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2Per-flow delay bound analysis based on a formalized microarchitectural model
X. Zhao, and Z. Lu. Networks on Chip (NoCS), 2013 Seventh IEEE/ACM International Symposium on, page 1-8. (April 2013)
10 years ago by @eberle18
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1Mathematical Formalisms for Performance Evaluation of Networks-on-chip
A. Kiasari, A. Jantsch, and Z. Lu. ACM Comput. Surv., 45 (3): 38:1--38:41 (July 2013)
10 years ago by @eberle18
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2Limiting Worst-Case End-to-End Latency When Traffic Increases in a Switched Avionics Network
M. Nam, E. Seo, L. Sha, K. Park, and K. Kang. Embedded and Real-Time Computing Systems and Applications (RTCSA), 2011 IEEE 17th International Conference on, 1, page 285-294. (August 2011)
10 years ago by @eberle18
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2Bounding End-to-End Delay for Real-Time Environmental Monitoring in Avionic Systems
D. Jin, J. Ryu, J. Park, J. Lee, H. Shin, and K. Kang. Advanced Information Networking and Applications Workshops (WAINA), 2013 27th International Conference on, page 132-137. (March 2013)
10 years ago by @eberle18
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1FNOCEE: A framework for NoC evaluation by FPGA-based emulation

2Fault-tolerant routing for on-chip network without using virtual channels

2Packet logging mechanism for adaptive online fault detection on Network-on-Chip

1A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

2Test Configurations for Diagnosing Faulty Links in NoC Switches

2On-line fault detection and location for NoC interconnects

2Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks

1Schedulability Analysis and Task Mapping for Real-time On-chip Communication

1Smart Reliable Network-on-Chip

1Crosstalk- and SEU-Aware Networks on Chips

2Low Power Error Resilient Encoding for On-Chip Data Buses

2Crosstalk avoidance coding for reliable data transmission of network on chips

1Markovian Models Based Stochastic Communication in Networks-in-Package

1Networks on chips: a new SoC paradigm

2Powering Networks on Chips: Energy-efficient and Reliable Interconnect Design for SoCs

2A brief overview of the challenges of the multicore roadmap

2Per-flow delay bound analysis based on a formalized microarchitectural model

1Mathematical Formalisms for Performance Evaluation of Networks-on-chip

2Limiting Worst-Case End-to-End Latency When Traffic Increases in a Switched Avionics Network

2Bounding End-to-End Delay for Real-Time Environmental Monitoring in Avionic Systems

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