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Test Configurations for Diagnosing Faulty Links in NoC Switches.

, , and . ETS, page 29-34. IEEE Computer Society, (2007)

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Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation., , and . ISCAS, page 1-5. IEEE, (2018)Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells., , and . DDECS, page 21-26. IEEE, (2018)Laboratory framework TEAM for investigating the dependability issues of microprocessor systems., , , and . EWME, page 80-83. IEEE, (2014)Test Generation for Digital Systems Based on Alternative Graphs.. EDCC, volume 852 of Lecture Notes in Computer Science, page 151-164. Springer, (1994)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE Computer Society, (2010)Functional Built-In Self-Test for processor cores in SoC., , , , and . NORCHIP, page 1-4. IEEE, (2012)On automatic software-based self-test program generation based on high-level decision diagrams., , and . LATS, page 177. IEEE, (2016)Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)