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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

C. Escuin, F. García-Redondo, M. Zahedi, P. Ibáñez, T. Monreal, V. Viñals, J. Llabería, J. Myers, J. Ryckaert, D. Biswas, and F. Catthoor. ICECS, page 1-5. IEEE, (2023)

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Angela Monreal

Gerhard Monreal

Alfred Monreal

Klaus Monreal

Simone Monreal

Other publications of authors with the same name

Hardware support for early register release.T. Monreal, V. Viñals, A. González, and M. Valero. IJHPCN, 3 (2/3): 83-94 (2005)Forecasting lifetime and performance of a novel NVM last-level cache with compression.C. Escuin, P. Ibáñez, T. Monreal, J. Llabería, and V. Viñals. CoRR, (2022)Speculative early register release.J. Alastruey, T. Monreal, V. Viñals, and M. Valero. Conf. Computing Frontiers, page 291-302. ACM, (2006)Near-optimal replacement policies for shared caches in multicore processors.J. Díaz, P. Ibáñez, T. Monreal, V. Viñals, and J. Llabería. J. Supercomput., 77 (10): 11756-11785 (2021)Dynamic Register Renaming Through Virtual-Physical Registers.T. Monreal, A. González, M. Valero, J. González, and V. Viñals. J. Instruction-Level Parallelism, (2000)Late Allocation and Early Release of Physical Registers.T. Monreal, V. Viñals, J. González, A. González, and M. Valero. IEEE Trans. Computers, 53 (10): 1244-1259 (2004)HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches.C. Escuin, A. Khan, P. Ibáñez, T. Monreal, V. Viñals, and J. Castrillón. DroneSE/RAPIDO@HiPEAC, page 53-58. ACM, (2022)ReD: A reuse detector for content selection in exclusive shared last-level caches.J. Díaz, T. Monreal, P. Ibáñez, J. Llabería, and V. Viñals. J. Parallel Distributed Comput., (2019)Light NUCA: A proposal for bridging the inter-cache latency gap.D. Gracia, T. Monreal, F. Vallejo, R. Beivide, and V. Viñals. DATE, page 530-535. IEEE, (2009)Delaying Physical Register Allocation through Virtual-Physical Registers.T. Monreal, A. González, M. Valero, J. González, and V. Viñals. MICRO, page 186-192. ACM/IEEE Computer Society, (1999)

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Disambiguation of "Monreal, Teresa"

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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Please choose a person to relate this publication to

Angela Monreal

Gerhard Monreal

Alfred Monreal

Klaus Monreal

Simone Monreal

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Monreal, Teresa"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Please choose a person to relate this publication to

Angela Monreal

Gerhard Monreal

Alfred Monreal

Klaus Monreal

Simone Monreal

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.