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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

C. Escuin, F. García-Redondo, M. Zahedi, P. Ibáñez, T. Monreal, V. Viñals, J. Llabería, J. Myers, J. Ryckaert, D. Biswas, and F. Catthoor. ICECS, page 1-5. IEEE, (2023)

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Benjamin Myers

Michael James

Audrein James

Katherine James

Adrian Myers

Other publications of authors with the same name

Development and Testing of Transcription Software for a Southern Min Spoken Corpus.J. Ruan, C. Hsu, J. Myers, and J. Tsay. IJCLCLP, (2012)Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, C. Lin, J. Wu and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)PROV-AQ: Provenance Access and QueryL. Moreau, O. Hartig, Y. Simmhan, J. Myers, T. Lebo, K. Belhajjame, and S. Miles. (2012)PROV-DM: The PROV Data ModelK. Belhajjame, R. B'Far, J. Cheney, S. Coppens, S. Cresswell, Y. Gil, P. Groth, G. Klyne, T. Lebo, J. McCusker and 4 other author(s). (2012)Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design.A. Savanth, A. Weddell, J. Myers, D. Flynn, and B. Al-Hashimi. ENSsys@SenSys, page 15-20. ACM, (2015)A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator.A. Savanth, A. Weddell, J. Myers, D. Flynn, and B. Al-Hashimi. IEEE J. Solid State Circuits, 54 (11): 3097-3106 (2019)Communicative Efficiency in Child Mandarin.J. Tsay, and J. Myers. PACLIC, Association for Computational Linguistics, (2018)8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications.J. Myers, A. Savanth, D. Howard, R. Gaddh, P. Prabhat, and D. Flynn. ISSCC, page 1-3. IEEE, (2015)Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor.H. Tamura, K. Kato, T. Ishizu, W. Uesugi, A. Isobe, N. Tsutsui, Y. Suzuki, Y. Okazaki, Y. Maehashi, J. Koyama and 5 other author(s). IEEE Micro, 34 (6): 42-53 (2014)Session 3 overview: Digital processors.T. Burd, J. Myers, and B. Nam. ISSCC, page 48-49. IEEE, (2017)

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Disambiguation of "Myers, James"

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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Please choose a person to relate this publication to

Benjamin Myers

Michael James

Audrein James

Katherine James

Adrian Myers

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Myers, James"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Please choose a person to relate this publication to

Benjamin Myers

Michael James

Audrein James

Katherine James

Adrian Myers

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.