( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

, , , , , , , , , , и . ICECS, стр. 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Angela Monreal

Gerhard Monreal

Klaus Monreal

Alfred Monreal

Simone Monreal

 

Другие публикации лиц с тем же именем

Hardware support for early register release., , , и . IJHPCN, 3 (2/3): 83-94 (2005)Forecasting lifetime and performance of a novel NVM last-level cache with compression., , , , и . CoRR, (2022)Speculative early register release., , , и . Conf. Computing Frontiers, стр. 291-302. ACM, (2006)Near-optimal replacement policies for shared caches in multicore processors., , , , и . J. Supercomput., 77 (10): 11756-11785 (2021)ReD: A reuse detector for content selection in exclusive shared last-level caches., , , , и . J. Parallel Distributed Comput., (2019)Light NUCA: A proposal for bridging the inter-cache latency gap., , , , и . DATE, стр. 530-535. IEEE, (2009)Delaying Physical Register Allocation through Virtual-Physical Registers., , , , и . MICRO, стр. 186-192. ACM/IEEE Computer Society, (1999)Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs., , , , , и . HPCA, стр. 179-192. IEEE, (2023)Hardware Schemes for Early Register Release., , , и . ICPP, стр. 5-13. IEEE Computer Society, (2002)Microarchitectural Support for Speculative Register Renaming., , , и . IPDPS, стр. 1-10. IEEE, (2007)