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Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , и 2 other автор(ы). DAC, стр. 13. ACM, (2019)Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories., , , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 733-746 (февраля 2023)Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM., , , , , , , , , и 7 other автор(ы). VLSI Circuits, стр. 194-. IEEE, (2019)New Memory Technology, Design and Architecture Co-Optimization to Enable Future System Needs.. VLSI-DAT, стр. 1. IEEE, (2019)Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems., , , , , , , , , и . ISCAS, стр. 1-4. IEEE, (2017)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , и 3 other автор(ы). DATE, стр. 103-108. IEEE, (2018)Liquid Memory and the Future of Data Storage., , , , , , , , , и 6 other автор(ы). IMW, стр. 1-4. IEEE, (2022)Impact of Mechanical Stress on the Electrical Performance of 3D NAND., , , , , , и . IRPS, стр. 1-5. IEEE, (2019)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , и . ISCAS, стр. 1-5. IEEE, (2023)A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1204-1214 (2017)