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TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.

, , , and . DAC, page 188-193. ACM, (2011)

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TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC., , , and . Commun. ACM, 57 (1): 107-115 (2014)On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective., , , , and . DAC, page 4:1-4:6. ACM, (2014)Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1694-1707 (2013)TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (8): 1194-1207 (2012)Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (7): 2109-2117 (2017)TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC., , , and . DAC, page 188-193. ACM, (2011)Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC., , , , and . ICCAD, page 563-570. IEEE Computer Society, (2011)A study of IR-drop noise issues in 3D ICs with through-silicon-vias., and . 3DIC, page 1-7. IEEE, (2010)Design for manufacturability and reliability for TSV-based 3D ICs., , , , , , , and . ASP-DAC, page 750-755. IEEE, (2012)Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs., , and . DAC, page 317-326. ACM, (2012)