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Basic building blocks for asynchronous packet routers., and . Great Lakes Symposium on VLSI, page 184-187. IEEE, (1994)Power Compiler: A Gate-Level Power Optimization and Synthesis System., and . ICCD, page 74-79. IEEE Computer Society, (1997)Low-latency asynchronous FIFO buffers., , , and . ASYNC, page 24-31. IEEE Computer Society, (1995)Asynchronous VLSI design.. University of Surrey, Guildford, UK, (1995)British Library, EThOS.Asynchronous packet routers., and . Interconnection Networks and Mapping and Scheduling Parallel Computations, volume 21 of DIMACS Series in Discrete Mathematics and Theoretical Computer Science, page 211-227. DIMACS/AMS, (1994)