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CMOS design of the tree arbiter element., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (4): 472-476 (1996)Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench., and . Inf. Process. Lett., 89 (6): 293-296 (2004)Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis., and . DAC, page 830-833. ACM, (2004)A Theory of Synchrony and Asynchrony., , and . Programming Concepts and Methods, page 459-478. North-Holland, (1990)User-Controlled, Auditable, Cross-Jurisdiction Sharing of Healthcare Data Mediated by a Public Blockchain., , , and . TrustCom, page 87-96. IEEE, (2020)Sequencer circuits for VLSI programming., and . ASYNC, page 82-90. IEEE Computer Society, (1995)Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.. ASYNC, page 83-94. IEEE Computer Society, (2007)Delay-Insensitive Interface Specification and Synthesis., and . DATE, page 169-173. IEEE Computer Society / ACM, (2000)Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review).. Softw. Test. Verification Reliab., 8 (1): 49 (1998)Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments., , and . Fundam. Informaticae, 70 (1-2): 21-48 (2006)