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Disambiguation of "Hanumolu, Pavan Kumar"

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A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.

, , , , , , , , and . VLSIC, page 352-. IEEE, (2015)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS., , , , and . ISSCC, page 182-183. IEEE, (2017)A 0.7V time-based inductor for fully integrated low bandwidth filter applications., , , , , , and . CICC, page 1-4. IEEE, (2017)An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing., , , , , , , and . CICC, page 171-174. IEEE, (2009)A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB., , and . CICC, page 443-446. IEEE, (2008)Area efficient phase calibration of a 1.6 GHz multiphase DLL., , and . CICC, page 1-4. IEEE, (2011)A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer., , , , and . CICC, page 1-4. IEEE, (2011)Digital clock and data recovery circuit design: Challenges and tradeoffs., , and . CICC, page 1-8. IEEE, (2011)An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW., , and . IEEE J. Solid State Circuits, 48 (2): 487-501 (2013)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery., , , , , and . IEEE J. Solid State Circuits, 46 (12): 3163-3173 (2011)