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Disambiguation of "Chaudhuri, Arjun"

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Advances in Design and Test of Monolithic 3-D ICs.

, , , , , , , , , and . IEEE Des. Test, 37 (4): 92-100 (2020)

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Selvam Arjunan

Arjun Roy

Arjun Chandra

Arjun Suresh

Arjun Chennu

 

Other publications of authors with the same name

Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4296-4309 (November 2023)Design Automation and Test Solutions for Monolithic 3D ICs., , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 21:1-21:49 (2022)Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs., , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 22:1-22:37 (2022)Machine Learning for Testing Machine-Learning Hardware: A Virtuous Cycle., , and . ICCAD, page 160:1-160:6. ACM, (2022)Structural Test Generation for AI Accelerators using Neural Twins., , and . IOLTS, page 1-6. IEEE, (2022)Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits., , , and . DATE, page 152-157. IEEE, (2021)Functional Criticality Classification of Structural Faults in AI Accelerators., , , and . ITC, page 1-5. IEEE, (2020)Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin∗., , , , , and . ITC, page 73-82. IEEE, (2021)Innovation Practices Track: Testability and Dependability of AI Hardware and Autonomous Systems., , , and . VTS, page 1. IEEE, (2023)Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1513-1526 (2020)