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Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs., , , and . ISLPED, page 26:1-26:6. ACM, (2022)Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis., , and . ISOCC, page 203-206. IEEE, (2021)Eliminating Minimum Implant Area Violations With Design Quality Preservation., , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (5): 611-621 (May 2023)Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs., , , , , and . ETS, page 1-6. IEEE, (2019)Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse., , , , , , , , , and 6 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (11): 2424-2437 (2020)Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement., , , and . MWSCAS, page 232-235. IEEE, (2021)Advances in Design and Test of Monolithic 3-D ICs., , , , , , , , , and . IEEE Des. Test, 37 (4): 92-100 (2020)Synthesizing Asynchronous Circuits toward Practical Use., and . ISVLSI, page 47-52. IEEE Computer Society, (2016)Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse., , , , , , , , , and 5 other author(s). DAC, page 178. ACM, (2019)Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees., and . ICCAD, page 691-696. IEEE, (2013)