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Disambiguation of "Banerjee, Sanmitra"

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Advances in Design and Test of Monolithic 3-D ICs.

, , , , , , , , , and . IEEE Des. Test, 37 (4): 92-100 (2020)

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Abhishek Banerjee

Prabuddha Banerjee

Mita Banerjee

Nandakishore Banerjee

Ishan Banerjee

 

Other publications of authors with the same name

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (3): 296-309 (March 2023)Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1513-1526 (2020)Advances in Design and Test of Monolithic 3-D ICs., , , , , , , , , and . IEEE Des. Test, 37 (4): 92-100 (2020)On the Impact of Uncertainties in Silicon-Photonic Neural Networks., , and . IEEE Des. Test, 40 (2): 82-89 (April 2023)Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis., , , and . ISVLSI, page 128-133. IEEE, (2022)RTL-to-GDS Design Tools for Monolithic 3D ICs., , , , , , , , , and . ICCAD, page 126:1-126:8. IEEE, (2020)Observation Point Insertion Using Deep Learning., , , , , , , and . ICCAD, page 161:1-161:8. ACM, (2022)Grading heart sounds through variational mode decomposition and higher order spectral features., , , and . I2MTC, page 1-5. IEEE, (2018)Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (2): 409-422 (2021)Modeling Silicon-Photonic Neural Networks under Uncertainties., , and . DATE, page 98-101. IEEE, (2021)