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CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.

, , , , и . ASYNC, стр. 62-72. IEEE Computer Society, (2000)

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Ken Lau

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Другие публикации лиц с тем же именем

Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems., и . IET Comput. Digit. Tech., 5 (4): 316-317 (2011)CAD Directions for High Performance Asynchronous Circuits., , , , , , и . DAC, стр. 116-121. ACM Press, (1999)Synthesis of asynchronous control circuits with automatically generated relative timing assumptions., , , и . ICCAD, стр. 324-331. IEEE Computer Society, (1999)Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits., , , , , , , и . ASYNC, стр. 80-. IEEE Computer Society, (1998)Fsimac: a fault simulator for asynchronous sequential circuits., , , , и . Asian Test Symposium, стр. 114-119. IEEE Computer Society, (2000)Automatic synthesis of computation interference constraints for relative timing verification., и . ICCD, стр. 16-22. IEEE Computer Society, (2009)Relative Timing., , и . ASYNC, стр. 208-218. IEEE Computer Society, (1999)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , и . ASYNC, стр. 60-70. IEEE Computer Society, (1999)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , и . ASYNC, стр. 62-72. IEEE Computer Society, (2000)Relative Timing Based Verification of Timed Circuits and Systems., , и . ASYNC, стр. 115-124. IEEE Computer Society, (2002)