( en | de | ru )

 

Disambiguation of "Cortadella, Jordi"

Author of the publication

copydeleteadd this publication to your clipboard
CAD Directions for High Performance Asynchronous Circuits.

, , , , , , and . DAC, page 116-121. ACM Press, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alexander Jording

Guido Jordine

Jordi Serangeli

Jordi Serratosa

Ulrich Jordi

 

Other publications of authors with the same name

Buffer Placement and Sizing for High-Performance Dataflow Circuits., , , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (1): 4:1-4:32 (2022)Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 1186-1190 (2022)Elastic Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (10): 1437-1455 (2009)Time elastic digital systems and Petri Nets., and . ACSD, page 1-2. IEEE, (2008)RTL-Aware Dataflow-Driven Macro Placement., , , , and . DATE, page 186-191. IEEE, (2019)Automatic microarchitectural pipelining., , , and . DATE, page 961-964. IEEE Computer Society, (2010)Working-zone encoding for reducing the energy in microprocessor address buses., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 568-572 (1998)Designing a branch target buffer for executing branches with zero time cost in a RISC processor., and . Microprocess. Microprogramming, 24 (1-5): 573-580 (1988)Scheduling in a continuous area-time design space., , and . Microprocessing and Microprogramming, 32 (1-5): 199-206 (1991)A mechanism for reducing the cost of branches in RISC architectures., , and . Microprocess. Microprogramming, 24 (1-5): 565-572 (1988)