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Identifying Resistive Open Defects in Embedded Cells under Variations.

, and . J. Electron. Test., 39 (1): 27-40 (February 2023)

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Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms., , , and . EDCC, volume 1667 of Lecture Notes in Computer Science, page 339-350. Springer, (1999)Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits., and . FTCS, page 36-41. IEEE Computer Society, (1988)ETS 2015 best paper., and . ETS, page 1. IEEE, (2016)Tools and devices supporting the pseudo-exhaustive test., and . EURO-DAC, page 13-17. IEEE Computer Society, (1990)High Defect Coverage with Low-Power Test Sequences in a BIST Environment., , , , and . IEEE Des. Test Comput., 19 (5): 44-52 (2002)Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses., , , , and . ITC, page 1-10. IEEE, (2019)GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling., and . DATE, page 879-884. IEEE, (2020)Deterministic logic BIST for transition fault testing., , , and . IET Comput. Digit. Tech., 1 (3): 180-186 (2007)Deterministic BIST with Partial Scan., and . J. Electron. Test., 16 (3): 169-177 (2000)Hardware-optimal test register insertion., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (6): 531-539 (1998)