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Improving placement algorithms by using visualization tools., , , and . NEWCAS, page 1-4. IEEE, (2016)Leakage current analysis in static CMOS logic gates for a transistor network design approach., , and . PATMOS, page 107-113. IEEE, (2016)Cell placement on graphics processing units., , , and . SBCCI, page 87-92. ACM, (2007)Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing., , , , and . ISCAS, page 2549-2552. IEEE, (2013)Routing-Aware Incremental Timing-Driven Placement., , , , , , , and . ISVLSI, page 290-295. IEEE Computer Society, (2016)Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities., , , , and . ISVLSI, page 84-89. IEEE Computer Socity, (2013)Jezz: An Effective Legalization Algorithm for Minimum Displacement., , , and . SBCCI, page 19:1-19:5. ACM, (2015)Quadratic placement with single-iteration linear system solver., , and . SBCCI, page 109-112. ACM, (2011)Drive Strength Aware Cell Movement Techniques for Timing Driven Placement., , , , and . ISPD, page 73-80. ACM, (2016)Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing., , , and . SBCCI, page 220-225. ACM, (2006)