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Leakage current analysis in static CMOS logic gates for a transistor network design approach., , и . PATMOS, стр. 107-113. IEEE, (2016)Cell placement on graphics processing units., , , и . SBCCI, стр. 87-92. ACM, (2007)Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing., , , , и . ISCAS, стр. 2549-2552. IEEE, (2013)Improving placement algorithms by using visualization tools., , , и . NEWCAS, стр. 1-4. IEEE, (2016)Routing-Aware Incremental Timing-Driven Placement., , , , , , , и . ISVLSI, стр. 290-295. IEEE Computer Society, (2016)Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities., , , , и . ISVLSI, стр. 84-89. IEEE Computer Socity, (2013)Quadratic placement with single-iteration linear system solver., , и . SBCCI, стр. 109-112. ACM, (2011)Jezz: An Effective Legalization Algorithm for Minimum Displacement., , , и . SBCCI, стр. 19:1-19:5. ACM, (2015)Drive Strength Aware Cell Movement Techniques for Timing Driven Placement., , , , и . ISPD, стр. 73-80. ACM, (2016)Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing., , , и . SBCCI, стр. 220-225. ACM, (2006)