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Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices., , , , , , , , , and 4 other author(s). MICRO, page 105-121. ACM, (2023)CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs., , , and . IEEE Embed. Syst. Lett., 14 (4): 187-190 (2022)A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel 4th Gen Xeon Scalable Processors., , , , , , and . CoRR, (2023)OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming., , , and . IEEE Trans. Computers, 68 (12): 1802-1816 (2019)Reconstructing Out-of-Order Issue Queue., , , and . MICRO, page 144-161. IEEE, (2022)Parallel in-order execution architecture for low-power processor., , and . ISOCC, page 65-66. IEEE, (2017)INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core., , , , and . PACT, page 309-319. IEEE, (2023)A convertible neural processor supporting adaptive quantization for real-time neural networks., , , , and . J. Syst. Archit., (December 2023)CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows., , , and . HPCA, page 383-396. IEEE, (2020)ScaleCache: A Scalable Page Cache for Multiple Solid-State Drives., , , , , , , , and . EuroSys, page 641-656. ACM, (2024)