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Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?

, , and . J. Electron. Test., 17 (6): 509-527 (2001)

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A unified approach to the synthesis of fully testable sequential machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 39-50 (1991)Addendum to "Synthesis of robust delay-fault testable circuits: Theory"., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (4): 445-446 (1996)Code density optimization for embedded DSP processors using data compression techniques., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (7): 601-608 (1998)Multi-source Domain Adaptation in the Deep Learning Era: A Systematic Survey., , , , and . CoRR, (2020)Cross-Domain Sentiment Classification With Contrastive Learning and Mutual Information Maximization., , , , and . CoRR, (2020)If I could only design one circuit ...: technical perspective.. Commun. ACM, 59 (11): 104 (2016)An automated exploration framework for FPGA-based soft multiprocessor systems., , , and . CODES+ISSS, page 273-278. ACM, (2005)Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks., , and . ITC, page 887-896. IEEE Computer Society, (1991)DAGON: Technology Binding and Local Optimization by DAG Matching.. DAC, page 341-347. IEEE Computer Society Press / ACM, (1987)FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search., , , , , , , , , and . CoRR, (2018)