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In-order delivery approach for 2D and 3D NoCs., , , and . J. Supercomput., 71 (8): 2877-2899 (2015)Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing., , , , , and . IEEE Trans. Computers, 63 (3): 718-733 (2014)Efficient congestion-aware selection method for on-chip networks., , , , and . ReCoSoC, page 1-4. IEEE, (2011)A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers., and . Computing, 97 (6): 631-648 (2015)Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip., , and . J. Syst. Archit., 59 (7): 516-527 (2013)Traffic-aware performance optimization in Real-time wireless network on chip., , , , , and . Nano Commun. Networks, (2020)Throughput Maximization of DNN Inference: Batching or Multi-Tenancy?, , and . CoRR, (2023)Near LLC versus near main memory processing., , and . GPGPU@PPoPP, page 1:1-1:6. ACM, (2022)Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy., , and . DATE, page 1601-1604. EDA Consortium San Jose, CA, USA / ACM DL, (2013)CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks., , , , and . DATE, page 320-325. IEEE, (2012)