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Disambiguation of "Koide, Tetsushi"

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A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.

, and . Integr., 27 (1): 57-76 (1999)

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Tetsushi Hirano

Tetsushi Harada

 

Other publications of authors with the same name

A low-power video segmentation LSI with boundary-active-only architecture., , , , , and . ASP-DAC, page 13-14. ACM Press, (2005)Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN., , , , , , , , and . ISDCS, page 1-4. IEEE, (2019)An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture., , , , , , , , , and 6 other author(s). TENCON, page 467-470. IEEE, (2018)A new global routing algorithm for over-the-cell routing in standard cell layouts., , and . EURO-DAC, page 116-121. IEEE Computer Society, (1993)Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints., , , , and . ISCAS, page 2059-2062. IEEE, (1993)A Verification Algorithm for Logic Circuits with Internal Variables., , , and . ISCAS, page 1920-1923. IEEE, (1995)Application of Multi-ported CAM for Parallel Coding., , , , and . APCCAS, page 1859-1862. IEEE, (2006)Domain Adaptation with L2 constraints for classifying images from different endoscope systems., , , , , , , , , and 1 other author(s). CoRR, (2016)Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping., , , , , and . IEEE J. Solid State Circuits, 47 (6): 1448-1459 (2012)A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)