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Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory., , , и . ICCD, стр. 66-73. IEEE, (2021)The IANET Hardware Accelerator for Audio and Visual Data Classification., , , и . SoCC, стр. 48-53. IEEE, (2020)Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware., , , , и . SOCC, стр. 1-6. IEEE, (2022)A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects., , , , , и . SoCC, стр. 132-137. IEEE, (2017)POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications., , , , и . DSD, стр. 889-898. IEEE, (2022)Industrially proving the SPIRIT consortium specifications for design chain integration., , , , , , , , , и . DATE Designers' Forum, стр. 142-147. European Design and Automation Association, Leuven, Belgium, (2006)pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning., , , , , и . IEEE Comput. Archit. Lett., 19 (2): 118-121 (2020)CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs., и . SOCC, стр. 1-6. IEEE, (2023)FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications., , , , и . ACM Great Lakes Symposium on VLSI, стр. 207-211. ACM, (2023)A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 69-74. ACM, (2018)